1. Field of the Invention
The present invention relates to a memory and an operating method thereof. More particularly, the present invention relates to a P-type channel non-volatile memory and an operating method thereof, wherein a byte erase operation can be performed.
2. Description of Related Art
Since EEPROM among non-volatile memories can be used to store, read, or erase data many times, and data stored in EEPROM will not be lost if the power is cut off, EEPROM has become a memory device widely used in personal computers and electronic apparatuses.
The typical EEPROM employs a doped poly-silicon material for fabricating the floating gate and control gate. Moreover, in order to prevent the problem of data error due to the severe over-erase phenomenon when the typical EEPROM erases, a select gate made of doped poly-silicon is further disposed on the sidewalls of the control gate and the floating gate and above the substrate, i.e. one select transistor is disposed on one side of the memory unit.
Referring to FIG. 1, a double-layer poly-silicon MONOS (metal/oxide/nitride/oxide/semiconductor) EEPROM is disclosed in U.S. Pat. No. 5,703,388 granted to Wang et al. The EEPROM includes a substrate 1, a field oxide layer 3, an N-type lightly doped region 11, a silicon oxide layer 5, a select gate 7, an ONO layer 13 and a control gate 15. The silicon oxide layer 5 is disposed on the substrate 1, and the select gate 7 is disposed on the silicon oxide layer 5. The ONO layer 13 is disposed on the lightly doped region 11 and extends to the select gate 7.
The EEPROM proposed by Wang et al., is a double-layer gate structure. When this N-type channel memory performs the programming operation, the hot carriers tunnel to the ONO layer through the channel region, so that charges are stored in the silicon nitride layer. During the erasing operation, the carriers tunnel to the drain through the ONO layer, so that the charges are discharged through the silicon nitride layer. Since a double-layer poly-silicon is required to be formed, it is hard to be integrated with other CMOS logic processes, and incurs expensive process adjustment and manufacturing costs, thus it is not applicable to the embedded memory.
Additionally, in the typical EEPROM, the erasing operation is directed to erasing all memory cells connected to a whole array in parallel, or all the memory cells in a broad sector of an array. Therefore, the erasing operation cannot be used for easing single object bytes, but must erase a whole array or sector. And, any part of the sector that need not be erased, that is, other than the object byte, must be re-programmed. Thus, an erasing/re-programming cycling is needed. This erasing/re-programming cycling is time consuming, and also causes higher power consumption.